ADZS-BF533-EZLITE【PDF 13/64 页】KIT W/BOARD EVAL FOR ADSP-BF533

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ADSP-BF531 / ADSP-BF532 / ADSP-BF533

t NOM is the duration running at f CCLKNOM

t RED is the duration running at f CCLKRED

The percent power savings is calculated as:

% power savings = ? 1 – power savings factor ? ? 100%

VOLTAGE REGULATION

The Blackfin processor provides an on-chip voltage regulator

that can generate appropriate V DDINT voltage levels from the

V DDEXT supply. See Operating Conditions on Page 20 for regula-

tor tolerances and acceptable V DDEXT ranges for specific models.

Figure 7 shows the typical external components required to

complete the power management system. The regulator con-

trols the internal logic voltage levels and is programmable with

the voltage regulator control register (VR_CTL) in increments

of 50 mV. To reduce standby power consumption, the internal

voltage regulator can be programmed to remove power to the

processor core while keeping I/O power (V DDEXT ) supplied.

While in the hibernate state, I/O power is still being applied,

eliminating the need for external buffers. The voltage regulator

can be activated from this power-down state either through an

For further details on the on-chip voltage regulator and related

board design guidelines, see the Switching Regulator Design

Considerations for ADSP-BF533 Blackfin Processors (EE-228)

applications note on the Analog Devices web site ( www.ana-

log.com )—use site search on “EE-228”.

CLOCK SIGNALS

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors can

be clocked by an external crystal, a sine wave input, or a buff-

ered, shaped clock derived from an external clock oscillator.

If an external clock is used, it should be a TTL-compatible signal

and must not be halted, changed, or operated below the speci-

fied frequency during normal operation. This signal is

connected to the processor’s CLKIN pin. When an external

clock is used, the XTAL pin must be left unconnected.

Alternatively, because the processors include an on-chip oscilla-

tor circuit, an external crystal can be used. For fundamental

frequency operation, use the circuit shown in Figure 8 .

Blackfin

RTC wakeup or by asserting RESET, both of which initiate a

boot sequence. The regulator can also be disabled and bypassed

at the user’s discretion.

CLKOUT

EN

TO PLL CIRCUITRY

V DDEXT

(LOW-INDUCTANCE)

SET OF DECOUPLING

CAPACITORS

700

100μF

+

V DDEXT

CLKIN

XTAL

0 *

V DDEXT

1M

100nF

10μH

100μF

+

FDS9431A

+

V DDINT

18pF*

18pF*

FOR OVERTONE

OPERATION ONLY

10μF

100μF

LOW ESR

ZHCS1000

VR OUT

NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED

DEPENDING ON THE CRYSTAL AND LAYOUT. PLEASE

ANALYZE CAREFULLY.

SHORT AND LOW-

INDUCTANCE WIRE

NOTE: DESIGNER SHOULD MINIMIZE

TRACE LENGTH TO FDS9431A.

Figure 7. Voltage Regulator Circuit

VR OUT

GND

Figure 8. External Crystal Connections

A parallel-resonant, fundamental frequency, microprocessor-

grade crystal is connected across the CLKIN and XTAL pins.

The on-chip resistance between CLKIN and the XTAL pin is in

the 500 k ? range. Further parallel resistors are typically not rec-

ommended. The two capacitors and the series resistor shown in

Voltage Regulator Layout Guidelines

Regulator external component placement, board routing, and

bypass capacitors all have a significant effect on noise injected

into the other analog circuits on-chip. The VROUT1–0 traces

and voltage regulator external components should be consid-

ered as noise sources when doing board layout and should not

be routed or placed near sensitive circuits or components on the

board. All internal and I/O power supplies should be well

bypassed with bypass capacitors placed as close to the proces-

sors as possible.

Figure 8 fine tune the phase and amplitude of the sine fre-

quency. The capacitor and resistor values shown in Figure 8 are

typical values only. The capacitor values are dependent upon

the crystal manufacturer's load capacitance recommendations

and the physical PCB layout. The resistor value depends on the

drive level specified by the crystal manufacturer. System designs

should verify the customized values based on careful investiga-

tion on multiple devices over the allowed temperature range.

A third-overtone crystal can be used at frequencies above

25 MHz. The circuit is then modified to ensure crystal operation

only at the third overtone, by adding a tuned inductor circuit as

shown in Figure 8 .

Rev. I

|

Page 13 of 64 |

August 2013

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